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其它知识点

• 在Verilog HDL中，使用关键词posedge表示上升沿触发，使用关键词negedge表示下降沿触发。
• 开发版中单个数码管是共阴级，4位数码管相反 是 共阳极
• 开发版中8*8点阵屏是共阳极
• 开发版中 拨码开关 拨到左边是off 为1

引脚绑定

分频模块

if(count==6000000) //0.5s周期

if(count==12000000) //1s周期

module divclk(clkin,clkout);
    input clkin;
    output clkout;
    reg clkout;
    reg[25:0] count;
    always@(posedge clkin)
    begin
       count=count+1;
       if(count==6000000) //0.5s周期
       begin
         clkout=~clkout;
         count=0;
      end
    end
endmodule

Flag计数

module flagcount(clkin,flagout);
    input clkin;
    output[3:0] flagout;
    reg[3:0] flagout;
    always@(posedge clkin)
    begin
        flagout = flagout+1;
    end
endmodule

四个数码管显示相同数

module seg4(flagin,seg,sl);
    input[3:0] flagin;
    output[7:0] seg;
    output[3:0] sl;
    reg[7:0] seg;
    reg[3:0] sl;
    
    always
        sl=4'b0000;
        
    always@(flagin)
    begin
        case(flagin)
            4'h0:seg=8'hc0;//0
            4'h1:seg=8'hf9;//1
            4'h2:seg=8'ha4;//2
            4'h3:seg=8'hb0;//3
            4'h4:seg=8'h99;//4
            4'h5:seg=8'h92;//5
            4'h6:seg=8'h82;//6
            4'h7:seg=8'hf8;//7
            4'h8:seg=8'h80;//8
            4'h9:seg=8'h90;//8
            4'ha:seg=8'h88;//a
            4'hb:seg=8'h83;//b
            4'hc:seg=8'hc6;//c
            4'hd:seg=8'ha1;//d
            4'he:seg=8'h86;//e
            4'hf:seg=8'h8e;//f
        endcase
    end
endmodule

四位数码管分别显示

/*
 * 四位数码管显示三位不同数字
 * clk进24M
 */
module seg4Show3(clk,datain,slout,segout);
    input clk;
    input[9:0] datain;
    output[3:0] slout;
    output[7:0] segout;

    reg[3:0] disp_dat;
    reg[3:0] sl_reg;
    reg[7:0] seg_reg;
    reg[36:0] count;

    always@(posedge clk)
        count = count + 1;
    
    always@(count[14:13])
    begin
        case(count[14:13])
            2'h0:begin
                disp_dat = 4'b0001;
                sl_reg = 4'b1111;
            end
            2'h1:begin
                disp_dat = datain/100;
                sl_reg = 4'b1101;
            end
            2'h2:begin
                disp_dat = (datain%100)/10;
                sl_reg = 4'b1011;
            end
            2'h3:begin
                disp_dat = datain%10;
                sl_reg = 4'b0111;
            end
        endcase
    end
    
    always@(disp_dat)
    begin
        case(disp_dat)
            4'h0:seg_reg=8'hc0;//0
            4'h1:seg_reg=8'hf9;//1
            4'h2:seg_reg=8'ha4;//2
            4'h3:seg_reg=8'hb0;//3
            4'h4:seg_reg=8'h99;//4
            4'h5:seg_reg=8'h92;//5
            4'h6:seg_reg=8'h82;//6
            4'h7:seg_reg=8'hf8;//7
            4'h8:seg_reg=8'h80;//8
            4'h9:seg_reg=8'h90;//8
            4'ha:seg_reg=8'h88;//a
            4'hb:seg_reg=8'h83;//b
            4'hc:seg_reg=8'hc6;//c
            4'hd:seg_reg=8'ha1;//d
            4'he:seg_reg=8'h86;//e
            4'hf:seg_reg=8'h8e;//f
        endcase
    end
    assign segout = seg_reg;
    assign slout = sl_reg;

endmodule

按键防抖并且计数

/*
 * 按键消抖 分频处理
 */
module divclk24(clkin,clkout);
    input clkin;
    output clkout;
    reg clkout;
    reg[25:0] count;
    always@(posedge clkin)
    begin
       count=count+1;
       if(count==240000)
       begin
         clkout=~clkout;
         count=0;
      end
    end
endmodule

/*
 * clkin 分频处理后的信号
 * keyin 按键按下的信号标志
 * out 输出的计数标志 这里是10位 可以改成1位
 */
module getkey(clkin,keyin,out);
    input clkin;
    input keyin;
    output[9:0] out;
    reg[9:0] out;
    reg keyout;
    
    always@(posedge clkin)
        keyout=keyin;

    always@(negedge keyout)
    begin
       out=out+1;
       if(out==1000)
       begin
         out=0;
      end
    end
endmodule

1位Seg数码管 显示百位数字

/* 
 * 共阴数码管
 */
module display(datain,flagin,segout);
    input[9:0] datain;
    input[1:0] flagin;
    output[7:0] segout;
    reg[7:0] segout;

    always@(datain)
    begin
       case(flagin)
            2'd0:
           case(datain/100)
                0:segout=8'h3f;//0
                1:segout=8'h06;//1
                2:segout=8'h5b;//2
                3:segout=8'h4f;//3
                4:segout=8'h66;//4
                5:segout=8'h6d;//5
                6:segout=8'h7d;//6
                7:segout=8'h07;//7
                 8:segout=8'h7f;//8
                 9:segout=8'h6f;//9
                 default:segout=8'h0;
            endcase
          2'd1:
           case((datain/10)%10)
                0:segout=8'h3f|8'h80;//0
                1:segout=8'h06|8'h80;//1
                2:segout=8'h5b|8'h80;//2
                3:segout=8'h4f|8'h80;//3
                4:segout=8'h66|8'h80;//4
                5:segout=8'h6d|8'h80;//5
                6:segout=8'h7d|8'h80;//6
                7:segout=8'h07|8'h80;//7
                 8:segout=8'h7f|8'h80;//8
                 9:segout=8'h6f|8'h80;//9
                default:segout=8'h0;
           endcase
         2'd2:
           case(datain%10)
                0:segout=8'h3f;//0
                1:segout=8'h06;//1
                2:segout=8'h5b;//2
                3:segout=8'h4f;//3
                4:segout=8'h66;//4
                5:segout=8'h6d;//5
                6:segout=8'h7d;//6
                7:segout=8'h07;//7
                 8:segout=8'h7f;//8
                 9:segout=8'h6f;//9
                default:segout=8'h0;
           endcase
        endcase
    end
endmodule

8*8点阵显示汉字

/*
 * 点阵显示 4个汉字 '上''下''中''大0'
 * clkinshow：进24M时钟信号，用于刷新上电
 * flagin：进显示汉字间隔，处理过的计数标志
 * ldoa,ldob：出点阵的位码输出口、数据输出口
 *
 * Tip：里面的count[14:12]，是刷新上电的间隔，应该非常小，可自行设置
 * case(flagin)下面分支可以改成自己的汉字编码
 */
module Showmatrix(clkinshow,flagin,ldoa,ldob);
    output[7:0] ldoa,ldob;
    input[1:0] flagin;
    input clkinshow;
    
    reg[7:0] ldoa,ldob;
    reg[32:0] count;
    
    always@(posedge clkinshow)
        count = count+1;
    
    always@(count[14:12])
    begin
    case(count[14:12])//上电
            3'h0:ldoa=8'hfe;
            3'h1:ldoa=8'hfd;
            3'h2:ldoa=8'hfb;
            3'h3:ldoa=8'hf7;
            3'h4:ldoa=8'hef;
            3'h5:ldoa=8'hdf;
            3'h6:ldoa=8'hbf;
            3'h7:ldoa=8'h7f;
        endcase
    end
    
    always@(count[14:12])
    begin
        case(flagin)
        2'b00:
            begin
                case(count[14:12])//上
                    3'h0:ldob=8'hf7;
                    3'h1:ldob=8'hf7;
                    3'h2:ldob=8'hc7;
                    3'h3:ldob=8'hf7;
                    3'h4:ldob=8'hf7;
                    3'h5:ldob=8'hf7;
                    3'h6:ldob=8'h80;
                    3'h7:ldob=8'hff;
                endcase
            end
        2'b01:
            begin
                case(count[14:12])//中
                    3'h0:ldob=8'hf7;
                    3'h1:ldob=8'hf7;
                    3'h2:ldob=8'h80;
                    3'h3:ldob=8'hb6;
                    3'h4:ldob=8'h80;
                    3'h5:ldob=8'hf7;
                    3'h6:ldob=8'hf7;
                    3'h7:ldob=8'hff;
                endcase
            end
        2'b10:
            begin
                case(count[14:12])//下
                    3'h0:ldob=8'hff;
                    3'h1:ldob=8'h80;
                    3'h2:ldob=8'hf7;
                    3'h3:ldob=8'he7;
                    3'h4:ldob=8'hd7;
                    3'h5:ldob=8'hf7;
                    3'h6:ldob=8'hf7;
                    3'h7:ldob=8'hf7;
                endcase
            end
        2'b11:
            begin
                case(count[14:12])//大
                    3'h0:ldob=8'hf7;
                    3'h1:ldob=8'hf7;
                    3'h2:ldob=8'h80;
                    3'h3:ldob=8'hf7;
                    3'h4:ldob=8'hf7;
                    3'h5:ldob=8'heb;
                    3'h6:ldob=8'hdd;
                    3'h7:ldob=8'hbe;
                endcase
            end
        endcase
    end

endmodule

蜂鸣器播放'梁祝’音乐模块

module music(clk_24MHz,buzzout,high,med,low);
input clk_24MHz;    

output buzzout;    
output[2:0] high,med,low;
reg[2:0] high,med,low;
reg buzzout_reg;
reg[24:0] count1,count2;    
reg[20:0] count_end;    
reg[7:0] counter;
reg clk_4Hz;

always@(posedge clk_24MHz)  
    begin
      if(count1<25'd3000000)
        begin
          count1=count1+1; 
        end
      else
        begin
          count1=0;
          clk_4Hz=~clk_4Hz;
        end
    end

always@(posedge clk_24MHz)
    begin
        count2=count2+1;
        if(count2==count_end)
            begin
                count2=25'h0;
                buzzout_reg=!buzzout_reg;
            end
    end

always@(posedge clk_4Hz)
    begin
        case({high,med,low})
            9'b000000001:count_end=16'hbb9a;    
            9'b000000010:count_end=16'ha72f;    
            9'b000000011:count_end=16'h94f2;    
            9'b000000100:count_end=16'h8e78;    
            9'b000000101:count_end=16'h7d63;    
            9'b000000110:count_end=16'h6fb5;    
            9'b000000111:count_end=16'h637f;    
            9'b000001000:count_end=16'h5dfb;    
            9'b000010000:count_end=16'h53bb;    
            9'b000011000:count_end=16'h4a95;    
            9'b000100000:count_end=16'h4651;    
            9'b000101000:count_end=16'h3eb1;    
            9'b000110000:count_end=16'h37da;    
            9'b000111000:count_end=16'h31bf;    
            9'b001000000:count_end=16'h2ef2;    
            9'b010000000:count_end=16'h29d4;    
            9'b011000000:count_end=16'h2543;    
            9'b100000000:count_end=16'h232f;    
            9'b101000000:count_end=16'h1f58;    
            9'b110000000:count_end=16'h1bed;
            9'b111000000:count_end=16'h18df;
            default:count_end=16'hffff;    
        endcase
    end

always@(posedge clk_4Hz)
    begin
        if(counter==47) counter=0;
        else counter=counter+1;
        case(counter)
            0:{high,med,low}=9'b000000011;    
            1:{high,med,low}=9'b000000011;    
            2:{high,med,low}=9'b000000011;
            3:{high,med,low}=9'b000000011;
            4:{high,med,low}=9'b000000101;    
            5:{high,med,low}=9'b000000101;
            6:{high,med,low}=9'b000000101;
            7:{high,med,low}=9'b000000110;    
            8:{high,med,low}=9'b000001000; 
            9:{high,med,low}=9'b000001000;
            10:{high,med,low}=9'b000001000;
            11:{high,med,low}=9'b000010000;    
            12:{high,med,low}=9'b000000110;    
            13:{high,med,low}=9'b000001000; 
            14:{high,med,low}=9'b000000101;
            15:{high,med,low}=9'b000000101;    
            16:{high,med,low}=9'b000101000; 
            17:{high,med,low}=9'b000101000;
            18:{high,med,low}=9'b000101000;
            19:{high,med,low}=9'b001000000;
            20:{high,med,low}=9'b000110000; 
            21:{high,med,low}=9'b000101000;
            22:{high,med,low}=9'b000011000;
            23:{high,med,low}=9'b000101000; 
            24:{high,med,low}=9'b000010000;
            25:{high,med,low}=9'b000010000;
            26:{high,med,low}=9'b000010000;
            27:{high,med,low}=9'b000010000;
            28:{high,med,low}=9'b000010000;
            29:{high,med,low}=9'b000010000;
            30:{high,med,low}=9'b000010000;
            31:{high,med,low}=9'b000010000;
            32:{high,med,low}=9'b000010000;        
            33:{high,med,low}=9'b000010000;
            34:{high,med,low}=9'b000010000;
            35:{high,med,low}=9'b000011000;
            36:{high,med,low}=9'b000000111;
            37:{high,med,low}=9'b000000111;
            38:{high,med,low}=9'b000000110;
            39:{high,med,low}=9'b000000110;
            40:{high,med,low}=9'b000000101;
            41:{high,med,low}=9'b000000101;
            42:{high,med,low}=9'b000000101;
            43:{high,med,low}=9'b000000110; 
            44:{high,med,low}=9'b000001000;
            45:{high,med,low}=9'b000001000;
            46:{high,med,low}=9'b000010000; 
            47:{high,med,low}=9'b000010000;
        endcase
    end
assign buzzout=buzzout_reg;

endmodule